Management of memory array with magnetic random access memory (mram)

ABSTRACT

An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/902,650, filed May 24, 2013, by Mehdi Asnaashari and entitled“MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM)”,which is a continuation of U.S. patent application Ser. No. 13/708,582,filed on Dec. 7, 2012, by Mehdi Asnaashari, and entitled “HOST-MANAGEDLOGICAL MASS STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM)”,which is a continuation-in-part of U.S. patent application Ser. No.13/679,739, filed by Mehdi Asnaashari, on Nov. 16, 2012, and entitled“HOST-MANAGED LOGICAL MASS STORAGE DEVICE USING MAGNETIC RANDOM ACCESSMEMORY (MRAM)”.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to a storage device and particularly tomanagement of the memory array of storage device by a controller.

2. Description of the Prior Art

Memory media in a mass storage device is used partially by thecontroller of the device to store a variety of types of private data,i.e. data that is not intended for public access and is rather intendedfor a very limited access, in the memory media, that are critical to thedevice's performance and reliability. Examples of such data include bootcode and tables, among others. The controller uses the rest of thememory media to store data from a host. Some of the data from the hostare frequently accessed and are also critically important to theperformance of the host incorporating the mass storage device. Hence thecontroller's efficient management of these data is most critical inoptimizing the mass storage device's performance as well as providingpleasant user experience.

Controller private data, such as boot code, is not very large comparewith user data but it requires a reliable storage media. Another exampleof private data is tables that are managed by the controller to locatelogical block addresses within the memory array physical blockaddresses. These tables are most critical to functionality andperformance of the device and are frequently accessed, as such theyrequire media with high performance, reliability, and non-volatility.

Controllers sometimes store security parameters such as AES keys intheir private data area which also requires reliable media. The securitykeys are used to protect the data of the memory array (part of thememory media) of the mass storage device. Any corruption of the keyswill most likely render the storage device useless.

Certain host parameters, such as file allocation table (FAT) anddirectories are accessed and updated frequently as well and require amemory media type with high performance and high reliability for optimalperformance. Other types of host data such as pictures, songs and moviestypically require a very large amount of storage and occupy the majorityof the memory media of the storage device but they do not require asreliable nor high performance by the memory media.

Current mass storage devices commonly utilize NAND flash memories forthe storage media. NAND memories provide large amounts of storage at areasonable price point but they fail to provide all the attributesrequired by the controller for achieving high performance and reliablesystem. NAND flash memories are inherently slow with limited reliabilityand endurance which makes them unattractive for controllers requiringthose attributes.

NAND flash memory is a block-based non-volatile memory with each blockorganized into and made of various pages. After a block is programmed,it is erased prior to programming it again. Most flash memory requiressequential programming of pages within a block. Another limitation offlash memory is that blocks can be erased for a limited number of times,thus frequent erase operations reduce the life time of the flash memory.Accordingly, flash memory does not allow for in-place updates. That is,it cannot simply overwrite existing data with new data. The new data arewritten to an erased area (out-of-place updates) only, and the old dataare invalidated for reclamation in the future. This out-of-place updatecauses the coexistence of invalid (i.e. outdated) and valid data in thesame block. “Garbage collection”, as is well known to those in the art,is a process referred to in reclaiming the space occupied by invaliddata and where valid data is moved to a new block and the old block iserased. Garbage collection generally and undesirably results insignificant performance overhead as well as unpredictable operationallatency.

As mentioned above, flash memory blocks can be erased for a limitednumber of times. Wear leveling is the process commonly employed toimprove flash memory life time by evenly distributing erases over theentire flash memory (within a band). A typical Multi Level Cell_(MLC)NAND flash manufactured using 25 nano meter technology typically has aprogram/erase (PE) cycle in the range of 1500 to 3000 cycles. Theyrequire erasing prior to being programmed with typical programming timeor duration being approximately 10 milli seconds (ms) and a program timefor programming a 4 to 8 Kilo Byte page being approximately 1 to 2 ms.

Moreover, NAND flash memories are organized in large page sizes of 8 KBand 16 KB and block sizes of 512 KB to 1 MB. Large page size attributeof flash memories makes it undesirable for small I/O operations sincethe whole page has to be programmed in its entirety. Programming apartial page requires merging of the existing data on the page with thenew data and writing it to a new page. The old page will no longercontain valid data and has to be reclaimed eventually. Since the datacorresponding to the same logical address is written to a differentphysical address, controller has to also maintain a table that maps thelogical address to the physical address.

NAND flash memories, despite all their deficiencies, are neverthelessthe preferred medium of choice for solid state mass storage devicesbecause of their capacity to save large amounts of data at reasonableprices.

As such, to enhance user experience yet achieve cost effectiveness, itsbest to complement NAND flash memories with higher performance,reliability and endurance and perhaps more expensive types of media suchas MRAM in the same mass storage device. This allows the controller tooptimize its performance, reliability, and user experience by using thehigher grade media to store its critical data and host system data andusing the NAND flash memories to store host non-critical data.

The controller may divide the MRAM array of the mass storage device intoa number of partitions and assign them to its private area or user areaand utilize them accordingly.

What is needed is a storage device that takes advantage of the use ofdifferent types of memories, such as NAND and MRAM, and is reliable,efficient, yet cost-effective.

SUMMARY OF THE INVENTION

To overcome the limitations in the prior art described above, and toovercome other limitations that will become apparent upon reading andunderstanding the present specification, the present invention disclosesa method and a corresponding structure for a magnetic storage memorydevice that is based on current-induced-magnetization-switching havingreduced switching current in the magnetic memory.

Briefly, an embodiment of the invention includes a mass storage devicewith a storage media that includes magnetic random access memory (MRAM)devices with a NAND flash interface and NAND flash memory devices thatare coupled to the MRAM devices. The storage media is partitioned into ahybrid reserved area made of a combination of MRAM array NAND array andhybrid user area made of a combination of MRAM array and NAND array andfurther includes a controller with a host interface and flash interfacecoupled to the MRAM and NAND flash memory devices through a flashinterface.

These and other objects and advantages of the present invention will nodoubt become apparent to those skilled in the art after having read thefollowing detailed description of the preferred embodiments illustratedin the several figures of the drawing.

IN THE DRAWINGS

FIG. 1 shows a mass storage device 10, in accordance with an embodimentof the invention.

FIG. 2 shows further details of the hybrid reserved area 36 and hybriduser area 30, in accordance with another embodiment of the invention.

FIG. 3 shows an exemplary logical representation of hybrid reserved area36 and hybrid user area 30, in accordance with an embodiment of theinvention.

FIG. 4 shows exemplary logical representation of hybrid user area 30, inaccordance with an embodiment of the invention.

FIG. 5 shows exemplary types of data stored in each of the hybrid userarea 30 and hybrid reserved area 36, in accordance with an embodiment ofthe invention.

FIG. 6 shows a flow chart of the steps performed by the mass storagedevice 10, in accordance with a method of the invention.

FIG. 7 shows a flow chart of the steps performed by the mass storagedevice 10, in accordance with a method of the invention.

DETAILED DESCRIPTION OF THE VARIOUS EMBODIMENTS

In the following description of the embodiments, reference is made tothe accompanying drawings that form a part hereof, and in which is shownby way of illustration of the specific embodiments in which theinvention may be practiced. It is to be understood that otherembodiments may be utilized because structural changes may be madewithout departing from the scope of the present invention.

As will become evident, in some embodiments of the invention, MRAM andNAND Flash memories are combined in a mass storage device. Currently,MRAM devices are more costly than NAND flash memories and fail toprovide the capacities that NAND flash memories offer but they are muchfaster than NAND flash with better reliability and endurance. As such,MRAM devices can be used by controllers to store their critical datarequiring such attributes. NAND flash memories can provide large amountof storage at a lower cost and it can be used by controllers for storinguser data from hosts which require large amount of capacity with lowerperformance, reliability and endurance. Examples of critical data arecontroller's boot code, tables and data cache and host's File allocationtable, and directories and so on and examples of non-critical data arepictures, movies, videos, and so on.

MRAM devices are more expensive than NAND flash memories but they aremuch faster than NAND flash with better reliability and endurance andthey can be used to store critical data requiring such attributes. NANDflash memories can provide large amounts of storage at a lower cost forstoring user area which requires larger capacity with lower performance,reliability and endurance.

FIG. 1 shows a mass storage device 10, in accordance with an embodimentof the invention. The device 10 is shown to include a controller 14 withNAND flash interface circuit 15 and host interface 20, a flash interface16, and a storage media 18. The controller 14 is shown coupled to thestorage media 18 through the flash interface 16. The controller 14 isshown to include a NAND flash interface circuit 15.

The controller 14 can selectively utilize the different memories in themedia for storing different type of data and that is used primarily bythe controller 14 to manage the devices 22 and 24.

The storage media 18 is shown to include a number of NAND flash memorydevices 22 and a number of magnetic random access memory (MRAM) devices24. The storage media 18 includes hybrid reserved area 36 that is acombination of some portion of NAND array 32 and some portion of MRAMarray 34. The storage media 18 also includes hybrid user area 30 that isa combination of some portion of NAND array 32 and some portion of MRAMarray 34. The devices 22 is shown to include a NAND flash interfacecircuit 26 and NAND array 32. The NAND array 32 of storage media 18includes the NAND portion 36 a of hybrid reserved area 36 and the NANDportion 30 a of hybrid user area 30. The devices 24 is shown to includea NAND flash interface circuit 28, MRAM array 34, and MRAM array 34 ofstorage medias 18 includes the MRAM portion 36 b of hybrid reserved area36 and the MRAM portion 30 b of hybrid user area 30.

The hybrid reserved area 36 spans the MRAM devices 24 and the NAND flashmemory devices 22 with the MRAM portion 36 b being a portion of the MRAMdevices 24 and the NAND portion 36 a being a portion of the NAND flashmemory devices 22. Similarly, the hybrid user area 30 spans the MRAMdevices 24 and the NAND flash memory devices 22 with the MRAM portion 30b being a portion of the MRAM devices 24 and the NAND portion 30 a beinga portion of the NAND flash memory devices 22.

Alternatively, the hybrid reserved area 36 may be entirely a part of theMRAM portion 36 b. Similarly, in alternative embodiments, the hybriduser area 30 is entirely a part of the MRAM portion 30 b. In the casewhere both the hybrid reserved area 36 and the hybrid user area 30 areboth entirely a part of the MRAM devices 24, there is no need for theNAND devices 22.

The hybrid reserved area 36 is used to store information that is privatedata or data that is inaccessible to a user of the device 10. Examplesof private data include boot code, system data, Meta data, or tables.

Based on apriory information regarding the identity of a host that is touse the device 10, the controller 14 advantageously decides to storehost-provided and host-critical data in the MRAM portion of the hybriduser area 30. An example of this is in the case of a file allocationtable (FAT) file system, such as FAT16 or FAT32, where the controller 14stores the master boot record (MBR), partition boot record (PBR), FATs,and directories, all of which are frequently-accessed information andintended for lower logical block access (LBA) range of addresses, in thearea 30 b.

In the embodiment of FIG. 1, storage media 18 provides two types ofmemory devices with each having distinct and complementary attributeswith MRAM devices 24 being very high performance and reliable and NANDflash memory devices 22 providing the majority of the capacity for thestorage media 18.

To simplify integration of MRAM and NAND flash into a single device,MRAM device requires an interface that is compatible with the NAND flashinterface. Furthermore, most of the existing embedded mass storagecontrollers such as USB, MMC, and SD only support memories with NANDflash interface without any modification to the controller. Therefore, aMRAM device with NAND flash interface can be readily integrated with anexisting controller and NAND flash memories to create a mass storagedevice with different media types to address different systemrequirements.

MRAM memories will make up the very high performance and reliableportion of the memory media of the storage device and can be used by thecontroller for storing data requiring such attributes. NAND flash memoryportion of the memory media can be used by the controller for storinguser area and data types that do not have such stringent requirements.

While MRAM is fast and reliable, it does not require erasure prior tobeing written with a new data. As such, management of data in the MRAMportion of the memory media can be greatly simplified. Controller willno longer have to perform garbage collections and mapping of thatportion of the memory media which will further improve the performanceof the system utilizing these storage devices.

It would also improve the performance of small IO operations since thedata can be written over the existing data and thus eliminating themerge and eventual GC process.

Another advantage of having MRAM on the memory media is to store themetadata information. In most controller architecture such as SATA andmSATA, an external DRAM with either DDR2 or DDR3 interface is used tostore the metadata information to improve the system performance. Due tothe nature of MRAM, the controller can use the MRAM portion of thememory media to store metadata information and eliminate the controllercost associated with DDR interface as well as the external DRAMcomponent.

Other controllers such as USB and MMC/eMMC that typically do not requirethe external DRAM use NAND flash for storing the metadata information.These controllers can also use the MRAM portion of the memory media andfurther improve system performance.

MRAM having an interface compatible with NAND flash memories becomestransparent to the controllers already having the NAND interface andwith minor modifications to the firmware in the area of write, garbagecollections, and metadata management due to the MRAM portion of thememory media, system performance will increase substantially.

The MRAM portion 36 b can also be used by the controller 14 to cachehost data or data provided by a host. Controller 14 can write the hostdata in response to host write command to the MRAM portion 36 b andinform the host that the write command has completed. The controller 14can then, at its convenience, find an available physical location withinthe hybrid user area 30 and move the host data from the MRAM portion 36b to the hybrid user area 30, which advantageously reduces the commandcompletion latency substantially. In the event, there is no availablephysical location in the hybrid user area 30, the controller 14 performs‘garbage collection’ to make available space for storing information inthe hybrid user area 30 prior to moving host data from the MRAM portion36 b into the hybrid user area 30. In the meanwhile, if the host wishesto read data that the controller 14 has saved in the hybrid reservedarea 36 but not yet moved to the hybrid user area 30, the controller 14knows to access this data only from the hybrid reserved area 36. Thus,host data coherency is maintained.

In another embodiment of this invention, the controller 14 may also usethe MRAM portion 36 b to collect enough host data to perform a NANDflash full page program operation. As is well known, in a NAND flashfull page program operation, when host IO operations are smaller than apage program unit of the NAND flash memory, a controller has to eitherperform partial page programming, which involves merging of the old datawith the new data and is time consuming or save the data in its volatileSRAM/DRAM buffer and wait for additional commands from the host untilthere is enough data to perform a page program operation. Meanwhile, thecontroller cannot send the command completion to the host since the hostdata has not yet written to a persistent media. The process of mergingof the old data with the new data requires reading of the old data andappending the new data to the read old data and writing this, in itsentirety, to another physical location within the NAND flash memorydevice, which is not only time consuming and effects performance of thedevice but it also increases the number of NAND flash program/eraseoperation and adversely effects NAND flash reliability and endurance. Inthe meanwhile, if the host wishes to read data that the controller 14has saved in the reserved area MRAM portion 36 b but not yet moved tothe hybrid user area 30, the controller 14 knows to access this dataonly from the reserved area MRAM portion 36 b. Thus, host data coherencyis maintained.

The foregoing problem is minimized in the various embodiments of theinvention, by using the MRAM portion 36 b for caching host data, whichsubstantially improves command latency and system reliabilityparticularly in systems with lots of small IO operations because of thepersistent characteristic of MRAMs.

In some embodiments of the invention, as discussed and shown herein,MRAM memories are mapped into controller's reserved area and providevery high performance and reliable media for controller's criticalparameters requiring such characteristics. NAND flash memories can alsobe mapped into user area and be used for user data and data types thatdo not such stringent requirements. A combination of MRAM and NAND flashmemories can also be mapped into a hybrid user area and hybrid reservedarea and be used for systems that only require high reliability andperformance for some of the data being stored on it. Controller will usethe media type for storing its parameters and host data, based on theirattributes.

FIG. 2 shows further details of the physical representation of the NANDarray 32 of NAND flash memory devices 22 and the MRAM array 34 of MRAMdevices 24. The NAND array 32 of storage media 18 includes the NANDportion 36 a of hybrid reserved area 36 and the NAND portion 30 a ofhybrid user area 30. The MRAM array 34 of storage media 18 is shown madeof the NAND portion 36 b of hybrid reserved area 36 and the MRAM portion30 b of hybrid user area 30 in accordance with another embodiment of theinvention. The hybrid reserved area 36 and the hybrid user area 30 maybe constructed of different combination of the MRAM portion 36 b and 30b respectively and the NAND portion 36 a and 30 a.

FIG. 3 shows an exemplary logical representation of memory arrays ofhybrid reserved area 36 and hybrid user area 30 FIG. 2. The hybridreserved area 36 is made of mixed memory array; the MRAM portion 36 band the NAND portion 36 a and provides a mixed attribute reserved areato the controller 14 for storing its data. The hybrid user area 30 ismade of mixed memory array; the MRAM portion 30 b and the NAND portion30 a and provides a mixed attribute user area to the controller 14 forstoring host data.

FIG. 4 shows exemplary logical representation of different type ofmemory arrays of hybrid user area, in accordance with an embodiment ofthe invention. Each of the hybrid user area 54, 76, and 78 may be thehybrid user area 30 of FIG. 1. In FIG. 4, the hybrid user area 54 isshown to include the MRAM memory array portion 56 on the lower logicalblock addresses (LBAs) and the NAND memory array portion 58 at thehigher LBAs. The hybrid user area 76 is shown to include the MRAM memoryarray portion 62 in the middle of the LBA range and two NAND memoryarray portions 60 and 64 at the lower and the higher LBA range inaccordance with another embodiment of the invention. The hybrid userarea 78 is shown to include two MRAM memory array portions 68 and 72 attwo different LBA ranges and three NAND memory array portions 66, 70 and74 at the lower, middle and upper LBA range. These exemplary logicalrepresentations of different memory arrays of a hybrid user area are todemonstrate that the user area may of any size and combination of MRAMand NAND memory arrays. Furthermore, MRAM memory array portion and NANDmemory array portion of hybrid user area may be any size and occupyvarious portion of the hybrid user area logical address space range.

FIG. 5 shows exemplary types of data stored by the controller 14 inmemory arrays of each of the hybrid reserved area 36 and hybrid userarea 30, in accordance with an embodiment of the invention. The MRAMportion 36 b of hybrid reserved area 36 is shown, as an exemplaryembodiment, to include the boot code, tables and data cache which arefrequently accessed by the controller and effect system performance andthe NAND portion 36 a of the hybrid reserved area 36 is shown forexample to include non-essential controller data. The MRAM portion 30 bof hybrid user area 30 is shown for example to include FAT anddirectories which are frequently accessed by the host and effect systemperformance and the NAND portion 30 a of the hybrid user area 30 isshown for example to include data from host such as pictures, movie, andvideos.

FIG. 6 shows a flow chart 100 of the steps performed by the mass storagedevice 10, in accordance with a method of the invention. The steps ofFIG. 6 are generally performed by the controller 14 (FIG. 1). At step114, a write command to a LUN, typically provided by the host, isreceived by the controller 14 followed by the user data. At step 102,the user data received by the controller 14 is written to the MRAMportion of the reserved area of the device 24, or MRAM portion 36 b.Next, at step 104, a command is sent by the controller 14 to the hostthrough the host interface 20 indicating completion of the writing instep 102 and a pointer is set identifying the location of the user databeing in MRAM portion 36 b.

Next, at 106, a determination is made by the controller 14 as to whetheror not available space remains in the LUN that the user data wasintended for. If not, the process continues to step 112 where space inthe intended LUN is freed up by the controller 14 by performing garbagecollection, and if so, the process moves onto the step 108.

At step 108, user data is moved from the MRAM portion 36 b to theintended LUN and the pointer of step 104 is re-adjusted to point to thelocation in the LUN where the user data has been moved, and the processends at 110.

FIG. 7 shows a flow chart 120 of the steps performed by the mass storagedevice 10, in accordance with a method of the invention. At step 122, anew write command to a LUN is received from a host by the controller 14followed by user data. Next, a determination is made at 124 as towhether or not the host write command, received by the controller 14 atstep 122, is a write to a full-flash page, i.e. full-flash pageoperation. If so, the user data is written to the intended LUN and theprocess ends at step 134.

If the host write command is not a full-flash page, the processcontinues to step 128 where user data is written to the reserved areaMRAM portion 36 b and a command complete is sent to a host, by thecontroller 14, such as done at step 102 of FIG. 6 and a pointer is setidentifying the location of the user data being in MRAM portion 36 b.

Next, at 130, a determination is made as to whether or not enough datais been collected in the reserved area MRAM portion for a full-pageoperation. If so, user data is moved from the MRAM portion 36 b to theintended LUN and the pointer of step 128 is re-adjusted to point to alocation in the LUN where the user data has been moved, and the processends at 134. If there is not enough data for a full-page operation, thecontroller waits for the next write command from the host at step 122.

Although the present invention has been described in terms of specificembodiments, it is anticipated that alterations and modificationsthereof will no doubt become apparent to those skilled in the art. It istherefore intended that the following claims be interpreted as coveringall such alterations and modification as fall within the true spirit andscope of the invention.

What is claimed is:
 1. A mass storage device comprising: a storage mediahaving, one or more MRAM devices including a first interface circuit;one or more NAND flash memory devices including a second interfacecircuit; a hybrid reserved area spanning at least a portion of the oneor more NAND flash memory devices and at least a portion of the one ormore MRAM devices; and a controller coupled to the storage media, thecontroller being coupled to the one or more MRAM devices through thefirst interface circuit and to the one or more NAND flash memory devicesthrough the second interface circuit, wherein the controller uses thehybrid reserved area to store private data.
 2. The mass storage deviceof claim 1, wherein the controller being responsive to host data andoperable to cache the host data in the at least a portion of the one ormore MRAM devices.
 3. The mass storage device of claims 2, wherein thestorage media further includes a user area that spans at least anotherportion of the one or more NAND flash memory devices and the controlleris operable to move the cached host data to the user area.
 4. The massstorage device of claim 1, wherein the private data comprises acombination of tables, boot code, system data, or Meta data.
 5. A massstorage device comprising: one or more MRAM devices including a firstinterface circuit; one or more NAND flash memory devices including asecond interface circuit; a hybrid reserved area spanning at least aportion of the one or more MRAM devices; and a controller responsive tohost data and coupled to the one or more MRAM devices through the firstinterface circuit and to the one or more NAND flash memory devicesthrough the second interface circuit, wherein the controller uses thehybrid reserved area to cache the host data.
 6. The mass storage deviceof claim 5, wherein the controller further uses the hybrid reserved areato store tables.
 7. The mass storage device of claim 6, wherein thehybrid reserved area further spans at least a portion of the one or moreNAND flash memory devices and further wherein the controller is operableto maintain at least a portion of the tables in the at least a portionof the one or more NAND flash devices.
 8. The mass storage device ofclaims 7, wherein periodically at least a portion of the tables aremoved from the portion of the one or more MRAM devices to the portion ofthe one or more NAND flash memory devices.
 9. The mass storage device ofclaims 5, wherein further including a user area spanning at least aportion of the one or more NAND flash memory devices and wherein thecontroller is operable to move the cached host data to the user area.10. The mass storage device of claims 9, wherein the controller isoperable to move the cached host data to the user area.
 11. The massstorage device of claim 10, further wherein upon unavailability ofstorage space in the NAND flash memory devices, the controller beingoperable to perform ‘garbage collection’ to make space available in theNAND flash memory devices prior to moving the cached host data from theMRAM devices to the NAND flash memory devices.
 12. The mass storagedevice of claim 10, further wherein upon the cached host data beingre-written prior to being moved to the user area, the controller beingoperable to over write the cached host data.
 13. The mass storage deviceof claim 10, further wherein upon the cached host data being read priorto being moved to the user area, the controller being operable to readthe cached host data.
 14. The mass storage device of claim 10, whereinthe controller is operable to cache adequate host data to perform a NANDflash full page program operation on the user area.
 15. The mass storagedevice of claim 5, wherein the mass storage device further including astorage media coupled to the controller and including the one or moreMRAM devices and the one or more NAND flash memory devices.
 16. A massstorage device including a storage media having one or more MRAM deviceswith a NAND flash interface and a one or more NAND flash memory devicescoupled to the MRAM devices via the same interface, the mass storagedevice further including a controller responsive to host data and havinga host interface, the controller coupled to the MRAM devices and theNAND flash memory devices through the NAND flash interface and coupledto a host through the host interface, wherein the controller uses aportion of the one or more MRAM devices to cache the host data.
 17. Themass storage device of claim 16, wherein the controller further uses thehybrid reserved area to store tables.
 18. The mass storage device ofclaim 17, wherein the hybrid reserved area further spans at least aportion of the one or more NAND flash memory devices and wherein thecontroller is operable to maintain at least a portion of the tables inthe at least a portion of the one or more NAND flash devices.
 19. Themass storage device of claims 18, wherein. periodically at least aportion of the tables are moved from the portion of the one or more MRAMdevices to the portion of the one or more NAND flash memory devices. 20.The mass storage device of claims 16, wherein further including a userarea spanning at least a portion of the one or more NAND flash memorydevices and the controller is operable to move the cached host data tothe user area.
 21. The mass storage device of claim 20, wherein thecontroller is operable to cache adequate host data to perform a NANDflash full page program operation on the user area.
 22. A mass storagedevice including one or more MRAM devices with a first interface circuitand one or more NAND flash memory devices with a second interfacecircuit, the mass storage device further including a controller having ahost interface and being coupled to the one or more MRAM devices throughthe first interface circuit, the controller further being coupled to theone or more NAND flash memory devices through the second interfacecircuit and further being coupled to a host through the host interface,wherein the controller uses a portion of the one or more MRAM devices tocache the host data.
 23. The mass storage device of claim 22, whereinthe hybrid reserved area further spans at least a portion of the one ormore NAND flash memory devices and further wherein the controller isoperable to maintain at least a portion of the tables in the at least aportion of the one or more NAND flash devices.
 24. The mass storagedevice of claims 23, wherein periodically at least a portion of thetables are moved from the portion of the one or more MRAM devices to theportion of the one or more NAND flash memory devices.
 25. The massstorage device of claims 22, wherein further including a user areaspanning at least a portion of the one or more NAND flash memory devicesand further wherein the controller is operable to move the cached hostdata to the user area.
 26. The mass storage device of claim 25, furtherwherein upon unavailability of storage space in the NAND flash memorydevices, the controller being operable to perform ‘garbage collection’to make space available in the NAND flash memory devices prior to movingthe cached host data from the MRAM devices to the NAND flash memorydevices.
 27. The mass storage device of claim 25 further wherein uponthe cached host data being re-written prior to being moved to the userarea, the controller being operable to over write the cached host data.28. The mass storage device of claim 25, further wherein upon the cachedhost data being read prior to being moved to the user area, thecontroller being operable to read the cached host data.
 29. The massstorage device of claim 25, wherein the controller is operable to cacheadequate host data to perform a NAND flash full page program operationon the user area.
 30. The mass storage device of claim 25, wherein themass storage device further including a storage media coupled to thecontroller and including the one or more MRAM devices and the one ormore NAND flash memory devices.